LDF 1.00.00 DESIGNLDF;

DESIGN             BAS.LDF;
REVISION           1.0, 01-MAR-1994;
AUTHOR             'Paddy Strebel;
PROJECTNAME        Video-Signal Generator;

DESCRIPTION        Composite Video Signal Generator for Black and White
                   Television Monitor (BAS: Bild, Austast, Synch).
                   Clock Source: 8MHz Cristal Oscillator;

PART               ispLSI1016-60LJ;

OPTION ISP OFF;
OPTION SECURITY OFF;
OPTION PULLUP UNUSED;
OPTION Y1_AS_RESET ON;
OPTION MINIMIZE FASTMIN;


SYM GLB  A0  1  HOR;
  SIGTYPE PSYNC REG OUT;   // gaps in vsync, start of hsync (2us)
  SIGTYPE HSYNC REG OUT;   // hsync (4.75us), starting from psync
  SIGTYPE TSYNC REG OUT;   // hsync (2.25us) vsynch precharge
  SIGTYPE HHIDE REG OUT;   // set for 12us after start
  EQUATIONS
    PSYNC.CLK = OCLK;
    PSYNC.D =  X7 &  X6 &  X5 &  X4 &  X3 &  X2 &  X1    // 254..256
            # !X7 & !X6 & !X5 & !X4 & !X3                // 0..7
            # !X7 & !X6 & !X5 & !X4 &  X3 & !X2          // 8..11
            # !X7 & !X6 & !X5 & !X4 &  X3 &  X2 & !X1;   // 12..13
    HSYNC.CLK = OCLK;
    HSYNC.D = START & !X7 & !X6 & !X5                      // 0..31
            # START & !X7 & !X6 &  X5 & !X4                // 32..47
            # START & !X7 & !X6 &  X5 &  X4 & !X3 & !X2;   // 48..51
    TSYNC.CLK = OCLK;
    TSYNC.D = !X7 & !X6 & !X5;              // 0..31
    HHIDE.CLK = OCLK;
    HHIDE.D = START & !X7 & !X6                // 0..63
            # START & !X7 &  X6 & !X5;         // 64..95
  END;
END;

SYM GLB  A1  1  VER;
  SIGTYPE VSYNC REG OUT;  // 5..9 sync new half frame
  SIGTYPE TRAB REG OUT;   // 0..14 tsync instead of hsync
  SIGTYPE VHIDE REG OUT;  // set if line is black
  EQUATIONS
    VSYNC.CLK = OCLK;
    VSYNC.D = !V9 & !V8 & !V7 & !V6 & !V5 & !V4 & !V3 &  V2 & !V1 & V0  // 5
            # !V9 & !V8 & !V7 & !V6 & !V5 & !V4 & !V3 &  V2 &  V1  // 6..7
            # !V9 & !V8 & !V7 & !V6 & !V5 & !V4 &  V3 & !V2 & !V1; // 8..9
    TRAB.CLK = OCLK;
    TRAB.D = !V9 & !V8 & !V7 & !V6 & !V5 & !V4 & !V3               // 0..7
           # !V9 & !V8 & !V7 & !V6 & !V5 & !V4 &  V3 & !V2         // 8..11
           # !V9 & !V8 & !V7 & !V6 & !V5 & !V4 &  V3 & V2 & !V1    // 12..13
           # !V9 & !V8 & !V7 & !V6 & !V5 & !V4 &  V3 & V2 & V1 & !V0;  // 14
    VHIDE.CLK = OCLK;
    VHIDE.D = !V9 & !V8 & !V7 & !V6 & !V5                          // 0..31
            # !V9 & !V8 & !V7 & !V6 &  V5 & !V4                    // 32..47
            # !V9 & !V8 & !V7 & !V6 &  V5 &  V4 & !V3 & !V2 & !V1; // 48..49
  END;
END;

SYM GLB  A2  1  SYNC;
  SIGTYPE SYNC REG OUT;   // synch signal
  SIGTYPE HIDE REG OUT;   // set if trace is black
  EQUATIONS
    HIDE.CLK = OCLK;
    HIDE.D = HHIDE # VHIDE;
    SYNC.CLK = OCLK;
    SYNC.D = HSYNC & !PSYNC & !TRAB   // horizontal synch
           # VSYNC & !PSYNC           // vertical synch with hsynch gaps
           # TSYNC & !PSYNC &  TRAB;  // vsync precharge pulses
  END;
END;

SYM GLB  A3  1  BLK;
  SIGTYPE TBCK OUT;    // black text background
  SIGTYPE IBCK OUT;    // interlace bar background
  EQUATIONS
    TBCK = !START & !X7 & !V9 & !V8 &  V7 &  V6 & V5; // 256..383, 224..255
    IBCK = !START & !X7 & !V9 &  V8 & !V7 &  V6 & V5; // 256..383, 353..383
  END;
END;

SYM GLB  A4  1  TEXT;
  SIGTYPE BLACK OUT;   // black area of picture
  SIGTYPE WHITE OUT;   // white area of picture;
  SIGTYPE HBAR OUT;    // horizontal bar for text
  EQUATIONS
    BLACK = TBCK # IBCK;
    WHITE = TBCK & TEXT                    // text
          # IBCK & !X6 &  X5 & !HALF       // even lines
          # IBCK &  X6 & !X5 &  HALF       // odd lines
          # IBCK &  X6 &  X5;              // odd and even lines
    HBAR = X4 # X3 # X2;
  END;
END;

SYM GLB  A5  1  TEXT;
  SIGTYPE TEXT OUT;     // text "TEST" on black
  EQUATIONS
    TEXT = !V4 & !V3 & V2 & HBAR                    // top lines of TEST
         # !X6 & !X5 & V4 & X4 & !X3 & !X2          // stemms of T's
         # !X6 & !X5 & V3 & X4 & !X3 & !X2
         #  X6 &  X5 & V4 & X4 & !X3 & !X2
         #  X6 &  X5 & V3 & X4 & !X3 & !X2
         # !X6 &  X5 & V4 & !X4 & !X3 & X2          // downstroke of E
         # !X6 &  X5 & V3 & !X4 & !X3 & X2
         # !X6 &  X5 & V4 & !V3 & !V2 & HBAR        // midline of E
         # !X6 &  X5 & V4 & V3 & V2 & HBAR          // base line of E
         #  X6 & !X5 & !V4 & V3 & !X4 & !X3 & X2    // left down of S
         #  X6 & !X5 & V4 & X4 & X3 & X2            // right down of S
         #  X6 & !X5 & V4 & !V3 & !V2 & HBAR        // midline of S
         #  X6 & !X5 & V4 & V3 & V2 & HBAR;         // base line of S
  END;
END;

SYM GLB  A6  1  SIG;
  SIGTYPE [SIG0..SIG3] REG OUT; // 16 shades of gray
  EQUATIONS
    [SIG0..SIG3].CLK = OCLK;
    SIG0 = WHITE & !HIDE # !BLACK & !HIDE & X4;
    SIG1 = WHITE & !HIDE # !BLACK & !HIDE & X5;
    SIG2 = WHITE & !HIDE # !BLACK & !HIDE & V4;
    SIG3 = WHITE & !HIDE # !BLACK & !HIDE & V5;
  END;
END;

SYM GLB  B0  1  CLK;
  SIGTYPE LCLK OUT;   // 31250Hz = twice the line clock 
  EQUATIONS
    LCLK = !X7;
  END;
END;

SYM GLB  B1  1  CKDIV;
  SIGTYPE [X0..X3] REG OUT;
  EQUATIONS
    [X0..X3].CLK = OCLK;
    X0.D = X0 $$ (VCC);              // 4MHz
    X1.D = X1 $$ (X0);               // 2MHz
    X2.D = X2 $$ (X1 & X0);          // 1MHz
    X3.D = X3 $$ (X2 & X1 & X0);     // 500kHz
  END;
END;

SYM GLB  B2  1  CKDIV;
  SIGTYPE [X4..X7] REG OUT;
  EQUATIONS
    [X4..X7].CLK = OCLK;
    X4.D = X4 $$ (X3 & X2 & X1 & X0);                  // 250kHz
    X5.D = X5 $$ (X4 & X3 & X2 & X1 & X0);             // 125kHz
    X6.D = X6 $$ (X5 & X4 & X3 & X2 & X1 & X0);        // 62500Hz
    X7.D = X7 $$ (X6 & X5 & X4 & X3 & X2 & X1 & X0);   // 31250Hz
  END;
END;

SYM GLB  B3  1  VCNT;
  SIGTYPE [V0..V3] REG OUT;
  EQUATIONS
    [V0..V3].CLK = LCLK;
    [V0..V3].RE = EOF;
    V0.D = V0 $$ (VCC);              // 1
    V1.D = V1 $$ (V0);               // 2
    V2.D = V2 $$ (V1 & V0);          // 4
    V3.D = V3 $$ (V2 & V1 & V0);     // 8
  END;
END;

SYM GLB  B4  1  VCNT;
  SIGTYPE [V4..V7] REG OUT;
  EQUATIONS
    [V4..V7].CLK = LCLK;
    [V4..V7].RE = EOF;
    V4.D = V4 $$ (V3 & V2 & V1 & V0);                  // 16
    V5.D = V5 $$ (V4 & V3 & V2 & V1 & V0);             // 32
    V6.D = V6 $$ (V5 & V4 & V3 & V2 & V1 & V0);        // 64
    V7.D = V7 $$ (V6 & V5 & V4 & V3 & V2 & V1 & V0);   // 128
  END;
END;

SYM GLB  B5  1  VCNT;
  SIGTYPE [V8..V9] REG OUT;
  EQUATIONS
    [V8..V9].CLK = LCLK;
    [V8..V9].RE = EOF;
    V8.D  = V8  $$ (V7 & V6 & V5 & V4 & V3 & V2 & V1 & V0);        // 256
    V9.D  = V9  $$ (V8 & V7 & V6 & V5 & V4 & V3 & V2 & V1 & V0);   // 512
  END;
END;

SYM GLB  B6  1  CTRL;
  SIGTYPE EOF REG OUT;    // end of frame: reset V to 0 at 625
  EQUATIONS
    EOF.CLK = OCLK;
    EOF = V9 & !V8 & !V7 & V6 & V5 & V4 & !V3 & !V2 & !V1 & V0; // 625
  END;
END;

SYM GLB  B7  1  CTRL;
  SIGTYPE HALF REG OUT;   // 0: first half-frame 1: second half-frame
  SIGTYPE START OUT;      // set on first half of line
  EQUATIONS
    HALF.PTCLK = !V9;
    HALF.D = !HALF;
    START = !V0 & HALF # V0 & !HALF;
  END;
END;

SYM IOC  Y0  1  OCLK;
  XPIN CLK OCLK_ LOCK 11;
  IB11(OCLK, OCLK_);
END;

SYM IOC  IO8  1  HALF;
  XPIN IO HALF_ LOCK 16;
  OB11(HALF_, HALF);
END;

SYM IOC  IO9  1  SYNC;
  XPIN IO SYNC_ LOCK 17;
  OB21(SYNC_, SYNC);
END;

SYM IOC  IO0  1  SIG0;
  XPIN IO SIG0_ LOCK 18;
  OB11(SIG0_, SIG0);
END;

SYM IOC  IO1  1  SIG1;
  XPIN IO SIG1_ LOCK 19;
  OB11(SIG1_, SIG1);
END;

SYM IOC  IO2  1  SIG2;
  XPIN IO SIG2_ LOCK 20;
  OB11(SIG2_, SIG2);
END;

SYM IOC  IO3  1  SIG3;
  XPIN IO SIG3_ LOCK 21;
  OB11(SIG3_, SIG3);
END;

END;  //LDF DESIGNLDF